The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

May. 16, 2019
Applicant:

Ipower Semiconductor, Gilroy, CA (US);

Inventor:

Hamza Yilmaz, Gilroy, CA (US);

Assignee:

IPOWER SEMICONDUCTOR, Gilroy, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 21/308 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/266 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66734 (2013.01); H01L 21/266 (2013.01); H01L 21/28088 (2013.01); H01L 21/3086 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/4966 (2013.01); H01L 29/7813 (2013.01);
Abstract

A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly silicon oxide (IPO) layer. The IPO layer can be formed by either depositing a silicon oxide layer or thermally growing a poly silicon oxide layer with minimal thickness variation. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.


Find Patent Forward Citations

Yilmaz, Hamza. (2020). Method of manufacturing shielded gate trench mosfet devices (U.S. Patent No. 10777661). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10777661

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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