The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Aug. 31, 2017
Sharp Kabushiki Kaisha, Sakai, Osaka, JP;
Jun Nishimura, Sakai, JP;
Yoshihito Hara, Sakai, JP;
Yoshimasa Chikama, Sakai, JP;
Yukinobu Nakata, Sakai, JP;
SHARP KABUSHIKI KAISHA, Sakai, JP;
Abstract
Provided is an active matrix substrate () that includes multiple inspection TFTs (Q) that are arranged in a non-display area (), and an inspection circuit () that includes multiple inspection TFTs (Q). At least one or more of the multiple inspection TFTs (Q) are arranged within a semiconductor chip mounting area (R) in which a semiconductor chip is mounted. Each of the multiple inspection TFTs (Q) includes a semiconductor layer, a lower gate electrode (FG) that is positioned on a side of the substrate of the semiconductor layer with a gate insulation layer in between, an upper gate electrode (BG) that is positioned on a side opposite to the side of the substrate of the semiconductor layer with an insulation layer including a first insulation layer in between, and a source electrode and a drain electrode that are connected to the semiconductor layer.