The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Jul. 26, 2018
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventor:

Franck Julien, La Penne sur Huveaune, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 27/088 (2006.01); H01L 21/8236 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0883 (2013.01); H01L 21/8236 (2013.01); H01L 21/84 (2013.01); H01L 27/1207 (2013.01); H01L 29/42368 (2013.01);
Abstract

The disclosure relates to a method of simultaneous fabrication of an MOS transistor of SOI type, and of first and second transistors on bulk substrate, comprising: a) providing a semiconductor layer on an insulating layer covering a semiconductor substrate; b) forming a mask comprising, above the location of the second transistor, a central opening which is less wide than the second transistor to be formed; c) plumb with the opening, entirely etching the semiconductor layer and insulating layer, hence resulting in remaining portions of the insulating layer at the location of the second transistor; d) growing the semiconductor by epitaxy as far as the upper level of the semiconductor layer; e) forming isolating trenches; and f) forming the gate insulators of the transistors, the gate insulator of the second transistor comprising at least one part of the said remaining portions of the insulating layer.


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