The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Jun. 08, 2017
Applicant:

Sony Corporation, Tokyo, JP;

Inventor:

Tomoharu Ogita, Kanagawa, JP;

Assignee:

SONY CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/062 (2012.01); H01L 21/8234 (2006.01); H01L 27/146 (2006.01); H01L 27/088 (2006.01); H04N 5/374 (2011.01);
U.S. Cl.
CPC ...
H01L 21/8234 (2013.01); H01L 27/088 (2013.01); H01L 27/1469 (2013.01); H01L 27/14634 (2013.01); H01L 27/14645 (2013.01); H04N 5/374 (2013.01); H01L 27/14643 (2013.01);
Abstract

To prevent a leakage current in a semiconductor integrated circuit in which a plurality of semiconductor substrates is laminated with a through-silicon via. Into a silicon substrate, one of P-type impurities and N-type impurities is implanted at a predetermined concentration. Into a plurality of channels, the other of the P-type impurities and the N-type impurities is implanted at a higher concentration than the predetermined concentration on one surface of the silicon substrate. An electrode is formed in each of the plurality of channels. Into a well layer, the same impurities as in the silicon substrate are implanted at a higher concentration than the predetermined concentration between the other surface of the silicon substrate and the plurality of channels.


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