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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10777424 B1

PDFFull Text
Date of Patent:
Sep. 15, 2020

Filed:

Feb. 27, 2019

Method for manufacturing semiconductor device

Applicants:

Kabushiki Kaisha Toshiba, Minato-lu, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Minato-ku, Tokyo, JP;

Inventor:

Takeo Kubota, Nomi Ishikawa, JP;

Assignees:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Attorney:

White & Case LLP

Primary Examiner:

Eduardo A Rodela

Int. Cl.
CPC ...
H01L 21/321 (2006.01); H01L 21/306 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/167 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/225 (2006.01); H01L 21/324 (2006.01); H01L 21/02 (2006.01); H01L 27/11526 (2017.01); H01L 21/304 (2006.01); H01L 21/302 (2006.01); H01L 27/11512 (2017.01); H01L 27/11509 (2017.01); H01L 27/108 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3212 (2013.01); H01L 21/02002 (2013.01); H01L 21/02005 (2013.01); H01L 21/02008 (2013.01); H01L 21/02021 (2013.01); H01L 21/02532 (2013.01); H01L 21/2253 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/302 (2013.01); H01L 21/304 (2013.01); H01L 21/3043 (2013.01); H01L 21/30625 (2013.01); H01L 21/324 (2013.01); H01L 27/10897 (2013.01); H01L 27/1116 (2013.01); H01L 27/11509 (2013.01); H01L 27/11512 (2013.01); H01L 27/11526 (2013.01); H01L 29/063 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01);
Abstract

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a second layer covering a first layer on a first region of a semiconductor substrate. The semiconductor substrate includes the first region and a second region. The first layer covers the second region and a portion of the first region. First openings are formed. The method can include removing the first layer on the second region using the second layer as a mask. The method can include forming an impurity region including an n-type impurity in the second region. The method can include removing the second layer, and growing silicon layers inside the first openings and on the second region. In addition, the method can include polishing a portion of each of the silicon layers using the first layer as a stopper.

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