The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Nov. 21, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jun-Gyu Lee, Hwaseong-si, KR;

Sung-Whan Seo, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/16 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01); H01L 27/1157 (2017.01); G11C 5/14 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 5/146 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); H01L 27/1157 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); G11C 11/5671 (2013.01);
Abstract

A non-volatile memory device includes a substrate; a memory cell array on the substrate; a control logic circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit configured to, in response to the erase enable signal, output a first target voltage to the substrate as a substrate bias voltage during a first delay time and, after the first delay time, output the substrate bias voltage to the substrate while gradually increasing a level of the substrate bias voltage to that of an erase voltage having a higher level than the first target voltage; and a row decoder configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay time.


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