The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Jul. 06, 2018
Applicant:

SK Hynix Inc., Icheon, KR;

Inventors:

Seung-Gyu Jeong, Icheon, KR;

Jung-Hyun Kwon, Seoul, KR;

Won-Gyu Shin, Icheon, KR;

Do-Sun Hong, Icheon, KR;

Assignee:

SK hynix Inc., Icheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G06F 3/06 (2006.01); G11C 29/12 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 29/36 (2006.01); G11C 29/46 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 7/1006 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 13/0004 (2013.01); G11C 13/0061 (2013.01); G11C 13/0097 (2013.01); G11C 29/12015 (2013.01); G11C 29/36 (2013.01); G11C 29/46 (2013.01); G11C 11/5678 (2013.01); G11C 2207/229 (2013.01); G11C 2213/72 (2013.01);
Abstract

A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.


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