The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Apr. 08, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Seung-you Baek, Suwon-si, KR;

Han-sung Joo, Seoul, KR;

Ki-sung Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 11/56 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0035 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/5607 (2013.01); G11C 11/5678 (2013.01); G11C 11/5685 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); G11C 2013/0078 (2013.01); G11C 2211/5644 (2013.01); G11C 2213/32 (2013.01); G11C 2213/52 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01);
Abstract

A memory controller may control a resistive memory device including memory cells may control the resistive memory device to program the memory cells into a first resistance state, control the resistive memory device to read data from the memory cells that are programmed, receive bit error rates (BER) of the memory cells, occurring in a read operation, from the resistive memory device, may determine the number of program operations on the memory cells corresponding to the BER and may, based on the number of program operations that is determined, control the memory cells to be programmed into the first resistance state by using a write current having a current level higher than that of a minimum write current required for the memory cells to be changed into the first resistance state.


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