The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Apr. 16, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Riduan Khaddam-Aljameh, Zurich, CH;

Manuel Le Gallo-Bourdeau, Zurich, CH;

Abu Sebastian, Adliswil, CH;

Evangelos Stavros Eleftheriou, Rueschlikon, CH;

Pier Andrea Francese, Adliswil, CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/406 (2006.01); G11C 11/56 (2006.01); G11C 11/4096 (2006.01); G11C 11/16 (2006.01); G11C 11/405 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40622 (2013.01); G11C 11/1655 (2013.01); G11C 11/405 (2013.01); G11C 11/4096 (2013.01); G11C 11/5628 (2013.01);
Abstract

A memory array comprises a data block comprising N serially connected cells. Each cell of the cells comprises a memory element storing a respective bit of the word, a charge adding unit and a switching logic. The last cell of the cells is further configured to receive a sequence of M bits. The memory array further comprises an output block serially connected to the data block. The output block comprises a result accumulation unit. The memory array is configured to operate in accordance with a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits. The memory array is configured such that a successive and repetitive application of the three phases enables an application of a phase during each clock cycle of the M groups.


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