The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Jun. 27, 2019
Applicant:

Kabushiki Kaisha Nihon Micronics, Tokyo, JP;

Inventors:

Katsushi Mikuni, Tokyo, JP;

Ryuichi Yagisawa, Tokyo, JP;

Akitsugu Yamaguchi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/394 (2020.01); G01R 1/073 (2006.01); G01R 3/00 (2006.01); G06F 30/39 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G01R 1/07342 (2013.01); G01R 3/00 (2013.01); G01R 1/07307 (2013.01); G06F 30/39 (2020.01);
Abstract

A wiring board design support apparatus, in which a plurality of vias are arranged on a wiring board, includes a design information storage unit that stores design information of vias and wirings to be arranged on the wiring board, and a wiring board via arrangement unit that moves, on a basis of the design information, positions of lattice points arranged with same intervals in vertical and horizontal directions by a given moving amount in a vertical direction and a horizontal direction while alternately changing a moving direction in the horizontal direction of the lattice points for each row of the lattice and alternately changing a moving direction in the vertical direction of the lattice points for each column of the lattice, so as to arrange vias at positions of the lattice points after movement.


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