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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10776311 B1

PDFFull Text
Date of Patent:
Sep. 15, 2020

Filed:

Mar. 13, 2018

Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports

Applicant:

Azurengine Technologies Zhuhai Inc., Zhuhai OT, CN;

Inventors:

Jianbin Zhu, San Diego, CA (US);

Yuan Li, San Diego, CA (US);

Assignee:

AzurEngine Technologies Zhuhai Inc., Zhuhai, CN;

Attorney:

IPro, PLLC

Primary Examiner:

Keith E Vicary

Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 9/445 (2018.01); G06F 15/78 (2006.01); G06F 12/0815 (2016.01); G06F 9/34 (2018.01); G06F 9/38 (2018.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 15/8023 (2013.01); G06F 9/3001 (2013.01); G06F 9/3004 (2013.01); G06F 9/3009 (2013.01); G06F 9/30098 (2013.01); G06F 9/34 (2013.01); G06F 9/3808 (2013.01); G06F 9/3867 (2013.01); G06F 9/3885 (2013.01); G06F 9/44505 (2013.01); G06F 12/0815 (2013.01); G06F 13/1673 (2013.01); G06F 15/7821 (2013.01); G06F 15/7867 (2013.01); G06F 15/7871 (2013.01); G06F 15/7875 (2013.01); G06F 15/7878 (2013.01); G06F 15/7885 (2013.01); G06F 15/7889 (2013.01); G06F 15/8046 (2013.01); G06F 15/8061 (2013.01); G06F 15/8069 (2013.01); G06F 15/8092 (2013.01); G06F 2212/1021 (2013.01); Y02D 10/14 (2018.01);
Abstract

Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of reconfigurable units that may include a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of reconfigurable units may comprise a configuration buffer and a reconfiguration counter. The processor may further comprise a sequencer coupled to the configuration buffer of each of the plurality of reconfigurable units and configured to distribute a plurality of configurations to the plurality of reconfigurable units for the plurality of PEs and the plurality of MPs to execute a sequence of instructions.

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