The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

May. 01, 2018
Applicant:

Integrated Device Technology, Inc., San Jose, CA (US);

Inventors:

Shwetal Arvind Patel, San Jose, CA (US);

Andy Zhang, San Jose, CA (US);

Wen Jie Meng, San Jose, CA (US);

Chenxiao Ren, Fremont, CA (US);

Alejandro F. Gonzalez, Johns Creek, GA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G06F 1/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 2213/0016 (2013.01);
Abstract

An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.


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