The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Oct. 31, 2017
Sandisk Technologies Llc, Plano, TX (US);
Daniel Linnen, Naperville, IL (US);
Srikar Peesari, San Jose, CA (US);
Kirubakaran Periyannan, Santa Clara, CA (US);
Avinash Rajagiri, San Jose, CA (US);
Shantanu Gupta, Milpitas, CA (US);
Jagdish Sabde, Fremont, CA (US);
Ashish Ghai, San Jose, CA (US);
Deepak Bharadwaj, Santa Clara, CA (US);
SANDISK TECHNOLOGIES LLC, Addison, TX (US);
Abstract
A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.