The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Mar. 02, 2016
Applicant:
Mellanox Technologies Ltd., Yokneam, IL;
Inventors:
Idan Burstein, Karmiel, IL;
Diego Crupnicoff, Buenos Aires, AR;
Shlomo Raikin, Kibbutz Yassur, IL;
Michael Kagan, Zichron Yaakov, IL;
Assignee:
MELLANOX TECHNOLOGIES, LTD., Yokneam, IL;
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0831 (2016.01); G06F 3/06 (2006.01); G06F 12/128 (2016.01); G06F 13/28 (2006.01); G06F 13/42 (2006.01); G06F 15/173 (2006.01); G06F 12/0804 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0833 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/128 (2013.01); G06F 13/28 (2013.01); G06F 13/4282 (2013.01); G06F 15/17331 (2013.01); G06F 12/0804 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/154 (2013.01); G06F 2212/621 (2013.01);
Abstract
A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.