The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Mar. 05, 2019
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Seongbeom Kim, Sunnyvale, CA (US);

Haoqiang Zheng, Cupertino, CA (US);

Rajesh Venkatasubramanian, San Jose, CA (US);

Puneet Zaroo, Santa Clara, CA (US);

Assignee:

VMWARE, INC., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/45554 (2013.01); G06F 9/48 (2013.01); G06F 9/5033 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45583 (2013.01);
Abstract

Systems and methods for performing selection of non-uniform memory access (NUMA) nodes for mapping of virtual central processing unit (vCPU) operations to physical processors are provided. A CPU scheduler evaluates the latency between various candidate processors and the memory associated with the vCPU, and the size of the working set of the associated memory, and the vCPU scheduler selects an optimal processor for execution of a vCPU based on the expected memory access latency and the characteristics of the vCPU and the processors. The systems and methods further provide for monitoring system characteristics and rescheduling the vCPUs when other placements provide improved performance and efficiency.


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