The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Jun. 21, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Christopher Gonzalez, Shelburne, VT (US);

Bryan Lloyd, Austin, TX (US);

Balaram Sinharoy, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/312 (2018.01); G06F 9/355 (2018.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 12/1009 (2016.01); G06F 9/38 (2018.01); G06F 9/34 (2018.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/32 (2013.01); G06F 9/3824 (2013.01); G06F 9/3832 (2013.01); G06F 9/3834 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3855 (2013.01); G06F 12/1009 (2013.01); G06F 9/34 (2013.01); G06F 9/355 (2013.01); G06F 12/1027 (2013.01); G06F 2212/1016 (2013.01);
Abstract

Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.


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