The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Mar. 01, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventor:

Shuou Nomura, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G06F 1/30 (2006.01); G11C 8/12 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 1/30 (2013.01); G11C 5/141 (2013.01); G11C 5/144 (2013.01); G11C 8/12 (2013.01); G11C 11/5635 (2013.01); G11C 16/3445 (2013.01); G11C 16/3459 (2013.01); G11C 2211/5641 (2013.01);
Abstract

According to one embodiment, a memory system includes a nonvolatile first memory, a volatile second memory, a capacitor, and a memory controller. The nonvolatile first memory includes a storage region that includes a plurality of memory cells. The capacitor is configured to accumulate electric power. The memory controller writes first data stored in the volatile second memory to the storage region in a first mode, using a power supply from outside. The first mode is a mode in which one-bit data is written to each of the memory cells. The memory controller writes, upon stop of the power supply from the outside, the first data to the storage region in a second mode, using the electric power accumulated in the capacitor. The second mode is a mode in which one-bit data is written to each of the memory cells and is different from the first mode.


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