The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Mar. 21, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Kyung Ho Kim, Seongnam-si, KR;

Seong Young Lee, Hwaseong-si, KR;

Yong Hee Lee, Suwon-si, KR;

Byoung Sun Na, Seoul, KR;

Sun Kwun Son, Suwon-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 1/136227 (2013.01); H01L 27/1214 (2013.01); H01L 27/14605 (2013.01); H01L 27/14612 (2013.01); G02F 2001/134345 (2013.01); G02F 2001/136222 (2013.01); G02F 2201/40 (2013.01);
Abstract

A display device including: a substrate; a gate line disposed on the substrate to transmit a gate signal; a first reference voltage line spaced apart from the gate line to transmit a reference voltage; a second reference voltage line disposed on the gate line and the first reference voltage line and electrically connected to the first reference voltage line; an insulating layer disposed on the second reference voltage line; and a pixel electrode layer disposed on the insulating layer, wherein the pixel electrode layer includes a first pixel electrode having a first sub-pixel electrode disposed at a first side with respect to the gate line and a second sub-pixel electrode disposed at a second side opposite to the first side with respect to the gate line, and the second reference voltage line may overlap the first pixel electrode and may cross the first pixel electrode.


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