Programmable/configurable logic circuitry, control circuitry and method of dynamic context switching

Abstract

An integrated circuit comprising a field programmable gate array (FPGA) including a plurality of logic tiles wherein each logic tile includes circuitry including (i) logic circuitry and (ii) an interconnect network including a plurality of multiplexers. The FPGA further includes a robust memory cell including: three or more storage elements that are more than one time programmable to store a data state, majority detection circuitry to detect a majority data state stored in the three or more storage elements; and an output, coupled to the majority detection circuitry, to output mode select data which is representative of the majority data state stored in the storage elements. The FPGA also includes mode/function select circuitry to configure a mode of operation of at least a portion of the circuitry in one or more of the plurality of logic tiles based on the mode select data.