The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Sep. 24, 2019
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventor:

Nan-Jang Chen, Hsinchu, TW;

Assignee:

MediaTek Inc., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/11 (2006.01); H01P 3/08 (2006.01); H05K 1/05 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0219 (2013.01); H01P 3/08 (2013.01); H05K 1/0224 (2013.01); H05K 1/0227 (2013.01); H05K 1/05 (2013.01); H05K 1/0218 (2013.01); H05K 1/0298 (2013.01); H05K 1/11 (2013.01); H05K 1/18 (2013.01);
Abstract

A printed circuit board includes a substrate having a top surface and a bottom surface. First non-ground nets and a ground net are disposed within a specific region on the top surface. A second non-ground net and a split ground net are disposed on the bottom surface. The second non-ground net is electrically connected to one of the first non-ground nets through a first via hole in the substrate. The second non-ground net is isolated from the split ground net by a gap. An outermost insulating layer on the bottom surface of the substrate covers the second non-ground net and the split ground net. A conductive layer is disposed on the outermost insulating layer corresponding to the specific region of the substrate in which the first non-ground nets and the ground net are arranged, such that the conductive layer overlaps with the first non-ground nets.


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