The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Feb. 20, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Steven R. Carlough, Poughkeepsie, NY (US);

Susan M. Eickhoff, Hopewell Junction, NY (US);

Michael W. Harper, Round Rock, TX (US);

Michael B. Spear, Round Rock, TX (US);

Gary A. Van Huben, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/085 (2006.01); H03L 7/081 (2006.01); G06F 11/16 (2006.01); G06F 1/10 (2006.01); G06F 1/06 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/085 (2013.01); G06F 1/06 (2013.01); G06F 1/10 (2013.01); G06F 11/1604 (2013.01); H03L 7/081 (2013.01); H04L 7/0037 (2013.01);
Abstract

A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.


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