The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Sep. 13, 2017
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventors:

Joachim Joos, Gerlingen, DE;

Walter von Emden, Enigen Unter Achalm, DE;

Assignee:

Robert Bosch GmbH, Stuttgart, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); H01L 29/51 (2006.01); B60L 50/64 (2019.01); G11C 16/04 (2006.01); H01L 23/525 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 21/28 (2006.01); H01L 29/788 (2006.01); H01M 2/34 (2006.01); H01M 10/42 (2006.01);
U.S. Cl.
CPC ...
H01L 29/512 (2013.01); B60L 50/64 (2019.02); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); H01L 23/5252 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/7883 (2013.01); H01L 29/792 (2013.01); H01M 2/34 (2013.01); H01M 10/4257 (2013.01); H01M 2220/20 (2013.01);
Abstract

A MOS component includes a source area, a drain area, a body area, a channel area, and a gate element, the channel area and the gate element being electrically insulated with respect to one another by a total of at least three individual layers in the form of a first individual layer, a second individual layer, and a third individual layer. The second individual layer is designed in such a way that it may permanently store electric charges. The third individual layer, which is situated between the channel area and the second individual layer, has a greater equivalent oxide thickness than the first individual layer situated between the second individual layer and the gate element.


Find Patent Forward Citations

Loading…