The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Apr. 02, 2019
Applicant:

Sakai Display Products Corporation, Sakai-shi, Osaka, JP;

Inventors:

Yuta Sugawara, Sakai, JP;

Satoshi Michinaka, Sakai, JP;

Nobutake Nodera, Sakai, JP;

Takao Matsumoto, Sakai, JP;

Assignee:

SAKAI DISPLAY PRODUCTS CORPORATION, Sakai-shi, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/428 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1229 (2013.01); G02F 1/1368 (2013.01); H01L 27/1225 (2013.01); H01L 27/1285 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H01L 29/78696 (2013.01); G02F 2202/10 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01);
Abstract

A thin film transistor includes: a gate electrode supported on a substrate; a gate insulating layer that covers the gate electrode; an oxide semiconductor layer provided on the gate insulating layer and having a crystalline region, the crystalline region including a first region, a second region, and a channel region located between the first region and the second region, wherein the channel region, the first region and the second region overlap with the gate electrode with the gate insulating layer interposed therebetween; a protection insulating layer arranged on the oxide semiconductor layer so that the channel region is covered and the first region and the second region are exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region, wherein a crystallinity of the channel region is different from a crystallinity of the first region and the second region.


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