The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Jun. 10, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventor:

Venkataramana Gangasani, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0026 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01);
Abstract

A memory device includes: a memory cell array, multiple bit lines, a compensation circuit, a holding circuit, and a control logic circuit. The memory cell array includes multiple memory cells. Each of the bit lines is connected to at least one of the memory cells. Among the bit lines, a predetermined voltage is applied to selected bit lines connected to selected memory cells. The compensation circuit includes a sampling circuit that generates a sampling value by sensing a leakage current applied to non-selected memory cells from among the plurality of memory cells. The holding circuit compensates for a voltage applied to the selected bit lines, based on the sampling value. The control logic circuit outputs a sampling-enable signal that controls enabling of the sampling circuit and a holding-enable signal that controls enabling of the holding circuit.


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