The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Mar. 04, 2019
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Takatsugu Kusumi, Sakai, JP;

Takuya Watanabe, Sakai, JP;

Akira Tagawa, Sakai, JP;

Yasuaki Iwase, Sakai, JP;

Yohei Takeuchi, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G09G 3/3696 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01);
Abstract

The present application discloses a scanning signal line drive circuit capable of reducing power consumption and narrowing a picture-frame while ensuring high-speed scanning for image display. First and second gate driversare arranged to face each other via a display unit. Based on a DC buffer method, odd-numbered gate lines are driven by the first gate driverwhile even-numbered gate bus lines are driven by the second gate driver, and when each gate bus line GLi is to be brought into a non-selected state, charges are released from both ends thereof. For this purpose, for example, the end portion of the odd-numbered gate bus line on the first gate driver side is connected to a buffer made up of the activation and inactivation transistors M, ML, and the end portion of the odd-numbered gate bus line on the second gate driver side is connected to the inactivation auxiliary transistor MR.


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