The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Jun. 29, 2019
Applicant:

AU Optronics Corporation, Hsinchu, TW;

Inventors:

Che-Chia Chang, Hsinchu, TW;

Hsien-Chun Wang, Hsinchu, TW;

Pin-Miao Liu, Hsinchu County, TW;

Ming-Hung Chuang, Tainan, TW;

Ming-Hsien Lee, Hsinchu, TW;

Shin-Shueh Chen, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/10 (2006.01); G09G 3/36 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G02F 1/1368 (2013.01); G02F 1/13624 (2013.01); G02F 1/136213 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); G09G 3/3607 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); G02F 2001/13685 (2013.01); G09G 2300/0819 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/021 (2013.01);
Abstract

A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.


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