The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Mar. 14, 2019
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Katsuhiro Yoda, Kodaira, JP;

Mitsuru Tomono, Higashimurayama, JP;

Takahiro Notsu, Kawasaki, JP;

Makiko Ito, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/485 (2006.01); G06F 7/487 (2006.01); G06T 1/20 (2006.01); G06F 17/16 (2006.01); G06F 17/15 (2006.01); G06F 9/38 (2018.01); G06N 3/063 (2006.01); G06F 7/544 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 7/4876 (2013.01); G06F 7/485 (2013.01); G06F 7/5443 (2013.01); G06F 9/38 (2013.01); G06F 15/80 (2013.01); G06F 17/153 (2013.01); G06F 17/16 (2013.01); G06N 3/063 (2013.01); G06T 1/20 (2013.01);
Abstract

A processor includes: a plurality of processor cores; and an internal memory configured to be accessed from the plurality of processor cores, wherein an arithmetic circuit provided in any of the plurality of processor cores includes: a plurality of first registers provided in a first stage of the arithmetic circuit, a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder, an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and a synthesis circuit including a third adder and a third register.


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