The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Oct. 19, 2018
Applicant:

Avago Technologies International Sales Pte. Limited, Singapore, SG;

Inventor:

Nitin Vinay Isloorkar, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/947 (2013.01); H04L 12/24 (2006.01); H04L 12/801 (2013.01); H04L 12/26 (2006.01); H04L 12/743 (2013.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
H04L 49/25 (2013.01); H04L 41/22 (2013.01); H04L 43/028 (2013.01); H04L 43/12 (2013.01); H04L 45/7453 (2013.01); H04L 47/10 (2013.01); H04L 67/322 (2013.01);
Abstract

Flexible switch logic packet processing includes receiving a first packet associated with a particular traffic flow, generating a switching decision behavior in a first cycle of the particular traffic flow by selecting one or more processing floors of a programmable pipeline based on a received profile signal indicating a type of processing required for the first packet, and performing packet processing on the first packet using the selected one or more processing floors of the programmable pipeline. In some aspects, an ingress packet processor is configured to generate a first switching decision behavior using the selected processing floors of a first programmable pipeline in the ingress packet processor. In other aspects, an egress packet processor is configured to perform a packet action on the passed first received packet based on a second switching decision behavior using the selected processing floors of a second programmable pipeline in the egress packet processor.


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