The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Nov. 09, 2018
Applicant:

Regents of the University of Minnesota, Minneapolis, MN (US);

Inventors:

Soheil Mohajer, Plymouth, MN (US);

Zhiheng Wang, St Paul, MN (US);

Kiarash Bazargan, Plymouth, MN (US);

Sayed Abdolrasoul Faraji, Minneapolis, MN (US);

Assignee:

Regents of University of Minnesota, Minneapolis, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 7/16 (2006.01); H03M 13/29 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03M 7/165 (2013.01); H03M 13/2903 (2013.01); H03K 19/21 (2013.01);
Abstract

This disclosure describes techniques for performing computational operations on input unary bit streams using one or more scaling networks. In some examples, a device is configured to perform a digital computational operation, where the device includes a plurality of input wires and a plurality of output wires. Each input wire is configured to receive a respective input bit of an encoded input value, and each output wire is configured to output a respective output bit of an encoded output value. The device also includes scaling network circuitry configured to apply a function to the encoded input value by electrically routing at least one input wire of the plurality of input wires to at least two output wires of the plurality of output wires. The device can also include hybrid binary/unary computations.


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