The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Mar. 23, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Julian Haines, Dublin, IE;

Rhona Wade, Dublin, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/027 (2006.01); H03L 7/197 (2006.01); H03K 19/20 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1974 (2013.01); H03K 3/027 (2013.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01);
Abstract

An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.


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