The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

May. 09, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventor:

Ho Young Shin, Gunpo-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H03K 3/037 (2006.01); H03K 19/0185 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/14 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
H03K 3/037 (2013.01); H03K 19/018521 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/30 (2013.01);
Abstract

A latch circuit including: a first inverter having a first pull-up transistor connected between a first power supply node and a first output node, and a first pull-down transistor connected between a second power supply node and the first output node; a second inverter having a second pull-up transistor connected between the first power supply node and a second output node, and a second pull-down transistor connected between the second power supply node and the second output node; a first current control transistor connected between the first pull-up transistor and the first output node; a second current control transistor connected between the second pull-up transistor and the second output node; a third current control transistor connected between the first pull-down transistor and the first output node; and a fourth current control transistor connected between the second pull-down transistor and the second output node.


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