The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Jun. 06, 2018
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventor:

Paul Fest, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 49/02 (2006.01); H01L 27/06 (2006.01); H01C 7/00 (2006.01); H01C 17/00 (2006.01); H01L 21/70 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 28/20 (2013.01); H01C 7/006 (2013.01); H01C 17/006 (2013.01); H01L 21/707 (2013.01); H01L 23/5228 (2013.01); H01L 27/0629 (2013.01);
Abstract

A method is provided for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device. A first dielectric layer is deposited on an integrated circuit (IC) structure including conductive contacts, a resistive film (e.g., comprising SiCCr, SiCr, CrSiN, TaN, TaSi, or TiN) is deposited over the first dielectric layer, the resistive film is etched to define the dimensions of the resistive film, and a second dielectric layer is deposited over the resistive film, such that the resistive film is sandwiched between the first and second dielectric layers. An interconnect trench layer may be deposited over the second dielectric layer and etched, e.g., using a single mask, to define openings that expose surfaces of the IC structure contacts and the resistive film. The openings may be filled with a conductive interconnect material, e.g., copper, to contact the exposed surfaces of the conductive contacts and the resistive film.


Find Patent Forward Citations

Quick Actions:

Fest, Paul. (2020). Systems and methods for forming a thin film resistor integrated in an integrated circuit device (U.S. Patent No. 10763324). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10763324

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…