The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Mar. 05, 2019
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Shunpei Yamazaki, Tokyo, JP;

Yasuhiko Takemura, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); H01L 27/108 (2006.01); H01L 21/84 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01); G11C 5/10 (2006.01); G11C 11/401 (2006.01); H01L 29/786 (2006.01); G11C 11/408 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10808 (2013.01); G11C 5/10 (2013.01); G11C 11/401 (2013.01); G11C 11/4085 (2013.01); H01L 21/84 (2013.01); H01L 23/528 (2013.01); H01L 23/53228 (2013.01); H01L 27/0688 (2013.01); H01L 27/10805 (2013.01); H01L 27/10873 (2013.01); H01L 27/10882 (2013.01); H01L 27/10897 (2013.01); H01L 27/1207 (2013.01); H01L 28/91 (2013.01); H01L 29/7869 (2013.01);
Abstract

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.


Find Patent Forward Citations

Loading…