The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2020
Filed:
Sep. 26, 2017
Texas Instruments Incorporated, Dallas, TX (US);
Krishna Praveen Mysore Rajagopal, Santa Clara, CA (US);
James P Di Sarro, Plano, TX (US);
Mariano Dissegna, Plano, TX (US);
Lihui Wang, Cupertino, CA (US);
Ann Margaret Concannon, Palo Alto, CA (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.