The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Jun. 01, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Young-Hoon Son, Hwaseong-si, KR;

Jung-Hwan Choi, Hwaseong-si, KR;

Seok-Hun Hyun, Seongnam-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 25/10 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/486 (2013.01); H01L 21/76877 (2013.01); H01L 23/49827 (2013.01); H01L 23/5226 (2013.01); H01L 23/5384 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/072 (2013.01); H01L 25/105 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02379 (2013.01); H01L 2225/1047 (2013.01);
Abstract

A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.


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