The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2020
Filed:
Jul. 13, 2017
Applicant:
Seagate Technology Llc, Cupertino, CA (US);
Inventors:
Pritesh Pawaskar, Maharashtra, IN;
Yehuda Smooha, Allentown, PA (US);
Shrikrishna Nana Mehetre, Maharashtra, IN;
Assignee:
SEAGATE TECHNOLOGY LLC, Fremont, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/50 (2006.01); H01L 23/498 (2006.01); H01L 27/02 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/50 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 24/81 (2013.01); H01L 27/0292 (2013.01); H01L 27/0296 (2013.01); H01L 2224/80122 (2013.01); H01L 2224/81122 (2013.01);
Abstract
An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.