The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Apr. 26, 2019
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Shutesh Krishnan, Negeri Sembilan, MY;

Sw Wei Wang, Seremban, MY;

Ch Chew, Seremban, MY;

How Kiat Liew, Bukit Jalil, MY;

Fui Fui Tan, Seremban, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/00 (2006.01); H01L 21/306 (2006.01); H01L 23/482 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/306 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 23/3114 (2013.01); H01L 23/482 (2013.01); H01L 29/0657 (2013.01);
Abstract

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.


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