The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Feb. 06, 2019
Applicant:

Okamoto Machine Tool Works, Ltd., Gunma, JP;

Inventors:

Eiichi Yamamoto, Gunma, JP;

Takahiko Mitsui, Gunma, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/762 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/7624 (2013.01); H01L 21/76243 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01);
Abstract

An embodiment of the present disclosure provides a method of manufacturing a semiconductor apparatus, including the following steps. A) forming a semiconductor device element in a Si active layer of an insulating isolation Si substrate including the Si active layer, a buried insulating layer, and a Si supporting substrate arranged in this order; B) forming a plurality of through electrode holes penetrating the Si active layer and the buried insulating layer to reach a partial region of the Si supporting substrate in an element region layer including the formed semiconductor device element; C) forming a through silicon via by sequentially forming an insulating film, a barrier film, and a Cu film inside the through electrode hole to completely fill the through electrode hole; D) forming a multilayer wiring layer including a wiring layer connected to the semiconductor device element on an outer surface of the element region layer in which the through silicon via is formed; and E) exposing the Cu film of the through silicon via by removing the Si supporting substrate after forming the multilayer wiring layer.


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