The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Dec. 31, 2018
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Stephen Jones, San Francisco, CA (US);

Vivek Kini, Sunnyvale, CA (US);

Piotr Jaroszynski, Sunnyvale, CA (US);

Mark Hairgrove, San Jose, CA (US);

David Fontaine, Mountain View, CA (US);

Cameron Buschardt, Round Rock, TX (US);

Lucien Dunning, San Jose, CA (US);

John Hubbard, San Jose, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/14 (2006.01); G06T 1/20 (2006.01); G06F 9/50 (2006.01); G06F 12/109 (2016.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 9/5016 (2013.01); G06F 12/109 (2013.01); G06T 1/60 (2013.01);
Abstract

The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.


Find Patent Forward Citations

Loading…