The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

May. 06, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Win Naing Maung, Plano, TX (US);

Douglas Edward Wente, Murphy, TX (US);

Mustafa Ulvi Erdogan, Allen, TX (US);

Huanzhang Huang, Plano, TX (US);

Saurabh Goyal, Bangalore, IN;

Bhupendra Sharma, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/38 (2006.01); G06F 13/42 (2006.01); H04B 3/36 (2006.01);
U.S. Cl.
CPC ...
G06F 13/382 (2013.01); G06F 13/4282 (2013.01); H04B 3/36 (2013.01); G06F 2213/0042 (2013.01);
Abstract

Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.


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