The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Apr. 26, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Bartholomew Blaner, Shelburne, VT (US);

Jeffrey A. Stuecheli, Austin, TX (US);

Michael S. Siegel, Raleigh, NC (US);

William J. Starke, Round Rock, TX (US);

Curtis C. Wollbrink, Rochester, MN (US);

Kenneth M. Valk, Rochester, MN (US);

Lakshminarayana Arimilli, Austin, TX (US);

John D. Irish, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 13/16 (2006.01); G06F 9/38 (2018.01); G06F 12/0817 (2016.01); G06F 12/1027 (2016.01); G06F 12/1045 (2016.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 3/061 (2013.01); G06F 9/3877 (2013.01); G06F 12/0822 (2013.01); G06F 12/1027 (2013.01); G06F 12/1045 (2013.01); G06F 13/1668 (2013.01); G06F 13/28 (2013.01); G06F 9/45533 (2013.01); G06F 2212/608 (2013.01); G06F 2212/657 (2013.01);
Abstract

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.


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