The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Nov. 28, 2016
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Mudit Bhargava, Austin, TX (US);

Joel Thornton Irby, Austin, TX (US);

Vikas Chandra, Fremont, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/08 (2006.01); G06F 12/02 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0238 (2013.01); G11C 13/0002 (2013.01); G11C 13/0023 (2013.01); G11C 13/0035 (2013.01); G11C 13/0059 (2013.01); H04L 9/0891 (2013.01); H04L 9/0894 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/1056 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7211 (2013.01);
Abstract

A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.


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