The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Dec. 12, 2018
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Drazen Borkovic, Los Altos, CA (US);

Jindrich Zejda, Saratoga, CA (US);

Taemin Kim, Portland, OR (US);

Ron Diamant, Albany, CA (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/36 (2006.01); G06F 17/10 (2006.01); G06F 3/048 (2013.01); G06F 13/40 (2006.01); G06F 17/50 (2006.01); G06F 9/30 (2018.01); G06F 12/00 (2006.01); G06F 8/41 (2018.01); G06N 3/02 (2006.01); G06F 12/1081 (2016.01); G06F 12/06 (2006.01); G06F 12/0888 (2016.01); G06F 8/34 (2018.01); G06F 9/50 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 8/458 (2013.01); G06F 9/30087 (2013.01); G06F 9/30101 (2013.01); G06F 12/0607 (2013.01); G06F 12/0888 (2013.01); G06F 12/1081 (2013.01); G06N 3/02 (2013.01); G06F 8/34 (2013.01); G06F 9/30043 (2013.01); G06F 9/30167 (2013.01); G06F 9/4552 (2013.01); G06F 9/5016 (2013.01); G06F 2212/621 (2013.01);
Abstract

Provided are systems and methods for generating program code for an integrated circuit, where instructions in the code synchronize computation engines that support non-blocking instructions. In various examples, a computing device can receiving an input data set including operations to be performed by an integrated circuit device and dependencies between the operations. The input data set can include a non-blocking instruction, and an operation that requires that the non-blocking instruction be completed. The computing device can generate instructions for performing the operation including a particular instruction to wait for a value to be set in a register of the integrated circuit device. The computing device can further generate program code including the non-blocking instruction and the instructions for performing the operation, wherein the non-blocking instruction is configured to set the value in the register.


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