The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Nov. 17, 2017
Applicant:

Festo SE & Co. KG, Esslingen, DE;

Inventors:

Martin Gehrke, Weinstadt, DE;

Roland Kalberer, Kirchheim, DE;

Ralf Forcht, Wendlingen, DE;

Assignee:

FESTO SE & CO. KG, Esslingen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 9/02 (2006.01); F15B 13/08 (2006.01); F15B 20/00 (2006.01);
U.S. Cl.
CPC ...
G05B 9/02 (2013.01); F15B 13/085 (2013.01); F15B 13/086 (2013.01); F15B 13/0839 (2013.01); F15B 13/0846 (2013.01); F15B 13/0867 (2013.01); F15B 13/0896 (2013.01); F15B 20/00 (2013.01); F15B 2211/6336 (2013.01); F15B 2211/8755 (2013.01);
Abstract

A safety module for an automation system includes a communication interface designed for a signal-transmitting connection to a communication system, an output interface designed for a signal-transmitting connection to at least one user which can be fitted downstream and a processing device connected to the communication interface and the output interface and designed to process communication signals from the communication interface and to provide output signals to the output interface wherein the processing device is designed for a detection of an actual component behaviour, using a control command contained in a communication signal and a component measured value contained in a communication signal, and for a comparison of a presettable component behaviour to the actual component behaviour as well as for a provision of a safety-oriented output signal to the output interface at a presettable divergence between the presettable component behaviour and the actual component behaviour.


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