The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Aug. 21, 2019
Applicant:

Northrop Grumman Systems Corporation, Falls Church, VA (US);

Inventors:

William Robert Reohr, Severna Park, MD (US);

Randall M. Burnett, Catonsville, MD (US);

Randal L. Posey, Baltimore, MD (US);

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/195 (2006.01); H03K 19/17704 (2020.01); H03K 19/1776 (2020.01); H03K 19/17736 (2020.01); G06N 10/00 (2019.01); G11C 11/44 (2006.01);
U.S. Cl.
CPC ...
H03K 19/195 (2013.01); G06N 10/00 (2019.01); H03K 19/1776 (2013.01); H03K 19/17708 (2013.01); H03K 19/17736 (2013.01); G11C 11/44 (2013.01);
Abstract

Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers. Because JTLBSLAs and JTLBSFPGAs are RQL-compliant, they can also include RQL gates connected within or between them, without signal conversion circuitry.


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