The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Jun. 26, 2019
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Masahiko Arimura, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/22 (2006.01); H03K 5/1252 (2006.01); H03K 3/01 (2006.01); H03K 3/037 (2006.01); G06F 1/06 (2006.01); H03K 21/00 (2006.01); G06F 1/08 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); G06F 1/06 (2013.01); G06F 1/08 (2013.01); H03K 3/01 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01); H03K 21/00 (2013.01);
Abstract

A pulse generation circuit has: an edge detector detecting a pulse edge in an input signal to generate edge detection signals; a clock generator generating a clock signal according to the edge detection signals; a frequency divider dividing the frequency of the clock signal to generate a frequency-divided clock signal; an input pad for receiving a test mode switch signal from a tester; and an output pad for outputting the frequency-divided clock signal to the tester. The edge detector can generate the edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in the inverted clock signal obtained by inverting the logic level of the clock signal when the test mode switch signal is being fed in. The signal delay time in the edge detector is adjustable according to the period of the frequency-divided clock signal as measured by the tester.


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