The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Sep. 13, 2019
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Abdullah Ahmed, Scarborough, CA;

Jonas Weiland, Del Mar, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/26 (2006.01); H03F 3/45 (2006.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
H03F 1/26 (2013.01); H03F 3/45179 (2013.01); H03F 2200/135 (2013.01); H03F 2200/165 (2013.01); H03F 2200/21 (2013.01); H03F 2200/267 (2013.01); H03F 2200/294 (2013.01); H03F 2200/297 (2013.01); H03F 2200/387 (2013.01); H03F 2203/45031 (2013.01); H03F 2203/45084 (2013.01); H03F 2203/45116 (2013.01); H03F 2203/45118 (2013.01); H03F 2203/45151 (2013.01); H03F 2203/45244 (2013.01);
Abstract

In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load.


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