The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Feb. 19, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Ji Ung Pak, Suwon-si, KR;

Won Chul Lee, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/11 (2006.01); G11C 11/416 (2006.01); H01L 21/285 (2006.01); G11C 7/12 (2006.01); G11C 11/56 (2006.01); H01L 49/02 (2006.01); H01L 27/112 (2006.01); G11C 5/02 (2006.01); G11C 11/403 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10855 (2013.01); G11C 7/12 (2013.01); G11C 11/416 (2013.01); G11C 11/565 (2013.01); H01L 21/285 (2013.01); H01L 21/28568 (2013.01); H01L 27/10852 (2013.01); H01L 27/1116 (2013.01); H01L 27/11293 (2013.01); H01L 28/92 (2013.01); H01L 49/02 (2013.01); G11C 5/025 (2013.01); G11C 11/403 (2013.01); G11C 11/412 (2013.01); H01L 27/10814 (2013.01); H01L 28/60 (2013.01); H01L 28/90 (2013.01); H01L 28/91 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.


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