The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Nov. 27, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Yonghoon Kim, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/50 (2006.01); H01L 25/11 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/50 (2013.01); H01L 24/02 (2013.01); H01L 24/13 (2013.01); H01L 25/0652 (2013.01); H01L 25/071 (2013.01); H01L 25/112 (2013.01); H01L 24/16 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/17181 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14361 (2013.01);
Abstract

A semiconductor package includes a package substrate, a logic chip on the package substrate, a memory stack structure on the package substrate and including first and second semiconductor chips stacked along a first direction, and a first bump between the package substrate and the memory stack structure. The logic chip and the memory stack are spaced apart along a second direction, crossing the first direction, on the package substrate. The first semiconductor chip includes a through via electrically connected to the second semiconductor chip, a chip signal pad connected to the through via, and a first redistribution layer electrically connected to the chip signal pad and having an edge signal pad in contact with the first bump. A distance between the logic chip and the edge signal pad along the second direction is less than that between the logic chip and the chip signal pad.


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