The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Oct. 22, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Min Gi Hong, Hwaseong-si, KR;

Yong Kwan Lee, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01); H01L 23/18 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/18 (2013.01); H01L 23/3135 (2013.01); H01L 23/5385 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 25/50 (2013.01); H01L 2224/73257 (2013.01); H01L 2225/107 (2013.01);
Abstract

A semiconductor device package-on-package (PoP) includes a first package, a second package, an interposer, a first molding layer, and a second molding layer. The first package includes a first substrate and a first semiconductor chip on the first substrate. The second package is disposed on the first package and includes a second substrate and a second semiconductor chip on the second substrate. The interposer is disposed between the first package and the second package and connects the first package and the second package. A first molding layer fills a space between the first package and the interposer. A second molding layer covers an upper surface of the interposer.


Find Patent Forward Citations

Hong, Min. (2020). Package-on-package type semiconductor package and method for manufacturing the same (U.S. Patent No. 10756075). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10756075

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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